High performance analog-to-digital converters (ADCs) are now widely used in many applications, including RF receivers (e.g., radar) and electronic countermeasures, communication systems, test instrumentation and others, that handle large dynamic ranges of signal amplitudes of a high data rate signals.
Dynamic specifications for ADCs are typically expressed in the frequency domain, using Fast Fourier Transforms (FFTs) to derive the specifications. With reference to FIG. 1, an example fundamental input signal 100 is shown at its carrier frequency 102, and its power amplitude 104 is shown as less than the full scale range 106 of the associated ADC, providing headroom 108, which is important to avoid clipping of the input signal in the case of offsets from the ADC or input signal generator. Spurious-free dynamic range (SFDR) 110 of the ADC is often defined as the distance in dB from the fundamental input signal 100 peak amplitude 104 to the peak spur level 112 in the output frequency spectrum, which could represent noise and is not necessarily limited to harmonic components of the analog input signal 100. An average noise floor 114 may be derived from both the average noise of the ADC and the FFT operation itself. The noise performance of the ADC is expressed as signal-to-noise ratio, or SNR=6.02n+1.76+10 log(m/2), where n=ADC resolution, and in =FFT points, and the signal is the RMS (root mean square) power of the fundamental input signal 100, and the noise is the RMS sum of all non-fundamental harmonics in the Nyquist band, excluding DC. For a given sampling frequency, fS, the theoretical RMS quantization noise in the bandwidth of input frequencies from DC to fS/2 is given as q/√n, where q is the weight of the ADC's least significant bit (LSB) and n is the number of bits.
Two fundamental limitations to maximizing SFDR in a high-speed ADC are the distortion produced by its front end electronics (i.e., amplifier and sample-and-hold circuit) and that produced by nonlinearity in the transfer function of the encoder portion of the ADC. While little can be done externally to the ADC to significantly reduce the inherent distortion caused by its front end, differential nonlinearity (DNL) in the ADC's encoder transfer function can be reduced by the proper use of external techniques. With reference to FIGS. 2A and 2B, DNL error is generally defined as the difference between an actual transfer function step width 200 (e.g., resulting from comparison of the input signal 202 to a precise reference voltage 202a provided by a reference voltage ladder 204 at a comparator circuit 206a as shown in FIG. 2B) and the ideal value of 1 LSB 208 as shown in FIG. 2A, and is often due to mismatches in the ADC's resistance ladder 204 providing threshold reference voltages 204a-204n and its comparator circuits 206a-206n (in a typical 12-bit ADC, a linear voltage step, 1 LSB, is approximately 250 mV).
Even a small non-linearity in an ADC's transfer function can cause harmonics. Particularly, when input signal amplitude and quantization step feature the same order of magnitude, the distortion can be serious in ways that decrease SFDR by consuming headroom. Therefore, when input signal features small amplitude, DNL error must be reduced to increase the ADC's SFDR. A receiver with excellent SFDR is able to receive at maximum data rate even when receive signals are at the low amplitude range of the receiver. DNL errors effectively decrease a receiver's SFDR rating.
A well-known technique called dithering is often utilized to maximize SFDR. Dithering is the process of adding an uncorrelated signal, such as pseudo random noise (PRN) or broadband noise, to a desired analog signal prior to the analog input gate of the ADC. Although the injected dither does not eliminate the errors, it randomizes the DNL errors of the ADC, thereby eliminating the concentration of DNL errors at a small number of codes. This technique improves the resolution and linearity of the conversion by effectively smoothing the quantization errors of the ADC's transfer function.
The effect of quantization noise is even more pronounced in broadband data converters. Wider ADC operating bands result in more thermal noise being integrated and impacting dynamic range. As the demand for both linearity and bandwidth increases, a physical limit is being reached and only a tradeoff between the bandwidth and the dynamic range can be considered. On the other hand, higher speeds could be achieved with a lower number of bits, if dynamic performance issues can be addressed. Thus, as technologies evolve toward element-level digitization, the need increases for low cost dithering techniques that efficiently provide high linearity analog to digital conversion in a manner that does not consume headroom. That is dither uses up some of the ADC's dynamic range. Unless a mitigation process is employed the dither impacts and reduces the maximum size input analog signal.
In some systems dither is varied to improve stability of the quantizer, especially in delta-sigma (DS) data converters. Stability, which manifests as a rise in quantization noise or a latchup condition at saturation, can suffer in these converters that use feedback loops. Reducing the dither amplitude as a function of the size of the signal entering the quantizer (not the analog input signal in the case of DS converters) can improve stability but does not optimize the allowable size of the analog input signal.
In other systems the output of the ADC is measured and used to control the dither power but latency in this measurement precludes avoiding saturation of the ADC by subsequent inputs or requires much smaller dither power that may be needed to maximize linearity. The desired scenario is to input as much dither as needed to maximize linearity without impacting the maximum size analog input signal that can be accommodated by the ADC's headroom or dynamic range.